1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor memory having a capacitor such as DRAM (Dynamic Random Access Memory).
2. Description of the Background Art
Known among conventional semiconductor memories is a DRAM cell made up of a MOS (Metal-Oxide Semiconductor) transistor and a capacitor whose lower electrode is an impurity diffusion layer connected to a source/drain region of the MOS transistor (cf. National Publication of Translation No. 2004-527901 and Japanese Patent Application Laid-Open No. 2004-311853). A DRAM cell described in the National Publication of Translation No. 2004-527901 includes an isolation insulation film (field insulation film) provided in an upper surface of a semiconductor substrate with a recess (cavity) formed in its upper portion, and sidewalls of the semiconductor substrate are exposed by the recess. The capacitor of the DRAM cell extends to reach the sidewalls exposed by the recess, increasing the effective area of the capacitor to produce an increase in capacity.
The DRAM cell of such structure might be damaged with its upper portion unnecessarily etched in creating the above-mentioned recess. When the upper portion of the recess is damaged, the capacitor extending into the recess degrades in electric characteristics, resulting in degradation in reliability of the DRAM cell. Therefore, a method of manufacturing a DRAM cell capable of preventing unnecessary etching of the upper portion of a recess in which a capacitor is to be formed is proposed (cf. Japanese Patent Application Laid-Open No. 62-51249 (1987)).
Further, a technique of cutting down a substrate deeply to form a capacitor structure therein in order to increase the capacity of a capacitor of a DRAM cell (cf. Japanese Patent Application Laid-Open No. 5-315564 (1993)).
In the above-described DRAM cell, the recess in the isolation insulation film provided to increase the effective area of the capacitor has conventionally been at a depth about half the depth of an isolation trench. The deeper the recess, the larger the effective area of the capacitor, however, too deep recess will damage the isolation insulation film in functionality, causing a parasitic MOS transistor to be formed between adjacent cells. As a result, charge leakage occurs between the adjacent cells, which degrades the DRAM cell in reliability.
Further, forming the capacitor structure in a step different from the step of forming an element isolation section and a transistor section will significantly increase the number of manufacturing steps, which in turn increases chip costs.